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Videos uploaded by user “sigjobs”
UTMI 1
 
03:11
UTMI- physical interface of USB2.0, Introduction to UTMI
Views: 1338 sigjobs
CMOS 10
 
06:08
PMOS load line,CMOS inverter load characteristics,power dissipation.
Views: 2495 sigjobs
UTMI 2
 
05:01
UTMI- Introduction to UTMI,USB Block structure,Key features of UTMI.
Views: 863 sigjobs
Guidelines (VC)  - 1
 
03:00
General coding guidelinesin verilog . verilog event queue .event scheduling and re-triggering .stratified event queue .active events .verilog simulatiion reference model
Views: 546 sigjobs
usb 1
 
01:27
USB2. 0 RTL USB2. 0 architecture
Views: 640 sigjobs
System Verilog 1 - 13
 
04:42
Description of system verilog Variables,types of variables,type casting
Views: 1772 sigjobs
USB 2
 
04:44
USB 2. 0 RTL Verilog code- protocol de-assembling module,USB device top, reset FSM,USB protocol engine, signal descriptions
Views: 2376 sigjobs
Verification_Methodology_Manual - 2
 
04:11
verification environment layered verification environment architecture application of layered test bench architecture
Views: 928 sigjobs
CMOS 9
 
01:25
CMOS inverter,Pseudo nMOS.
Views: 2458 sigjobs
Synthesis and Simulation 1
 
06:42
Synthesis and simulation- RTL Coding Styles,problem with incomplete sensitivity list,full case and parallel case.
Views: 1213 sigjobs
UTMI 5
 
01:23
UTMI- Introduction to UTMI,UTMI Receive State machine,UTMI Transmit state machine.
Views: 407 sigjobs
System Verilog 2 - (sv_guid 2)
 
02:17
Implicit net declaration .Escaped identifiers in hierarchy paths.Methods to avoid the gotchas
Views: 364 sigjobs
FIFO 5
 
01:39
gray code counter .over flow .under flow
Views: 593 sigjobs
synthesis_verilog 4
 
07:27
if statements case statements casez statements casex statements fullcase &parallel case statements
Views: 371 sigjobs
System Verilog 1 - 12
 
09:10
Description on literal values and built in data types,advantages, compiler directive `define enhancement, external compilation unit declarations, macros,compilation unit declarations
Views: 2380 sigjobs
USB1_1
 
03:00
Technical Overview USB Physical Topology Tiered Star Topology USB Host USB Hub USB Physical Layer-Mechanical & Electrical USB Connectors USB Cables Signaling DC levels(FS/LS) Chirp/Speed Detection Handshake Signaling
Views: 1020 sigjobs
HDLC 4
 
05:34
pattern .ideal sequences .block diagram of HDLC .MC HDLC controller system
Views: 1395 sigjobs
CMOS 12
 
02:07
CMOS- Noise Margin,Source of Capacitance ,virtual capacitance.
Views: 3248 sigjobs
Verilog 5
 
04:51
Different in implementation with sequential and combinatorial process . casex and case
Views: 718 sigjobs
FPGA
 
09:18
Introduction .Fundamental concepts .The origin of FPGA .IC Implementation Methods .Anti-fuse technoilogies .PROM .SRAM-based technologies .ASIC and its types .Anti-fuse based FPGA's .Place and route .Programmable Fusible links .
Views: 9972 sigjobs
System Verilog 1 - 1
 
07:39
system verilog assertion .need for assertion .kinds of assertion .system verilog assertion layers property declaration layer assertion directive layer immediate assertion concurrent assertion sequences more on delays
Views: 32190 sigjobs
Combo 10
 
03:23
READ-ONLY MEMORY .ROM Memory Array
Views: 2029 sigjobs
FIFO 4
 
01:47
gray code patterns
Views: 1053 sigjobs
soc 9
 
08:42
Static Netlist Verification,Netlist verification,Bluetooth SOC Arbiter,Formal quivalence checking,Selecting an EC Solution
Views: 125 sigjobs
Verilog 4
 
05:11
Difference between full-case and parallel-case
Views: 563 sigjobs
USB 8
 
06:42
Verilog code- Packet assembling module, CRC checking.
Views: 380 sigjobs
System Verilog 1-16
 
04:29
Description on arrays,single dimensional arrays,packed arrays,unpacked arrays,
Views: 4299 sigjobs
CMOS 4
 
06:26
Diode,Reverse-bias,MOS transistors, Symbol of MOS transistors,Threshold voltage,Depletion Region,
Views: 4941 sigjobs
System Verilog 1-17
 
07:26
Description on arrays,Arrays of arrays,special arrays, structures, Unions,packed structure, unpacked structure,passing structure through ports,packed union,unpacked union
Views: 2833 sigjobs
System Verilog 1-25
 
03:40
Sample programs on FSM using System verilog
Views: 1424 sigjobs
FIFO 1
 
07:05
simulation and synthesis technique for asynchronous FIFO .introduction . passing multiple asynchronous signal
Views: 4594 sigjobs
SOC 33
 
06:12
ASB master .directed random testing . code coverage .different types of coverage .examples of coverage
Views: 103 sigjobs
FIFO 3
 
04:38
read pointer .write pointer .empty flag .fifo full .fifo empty
Views: 4022 sigjobs
System Verilog 1 - 7
 
08:03
embedding concurrent assertions in procedural code .clock resolution . binding properties to scopes or instances .system verilog assertion layers . summary
Views: 4757 sigjobs
sta 1
 
07:45
sta basics .propagation delays .setup/hold time .skew .metastability .maximum propagation delay .typical propagation delay .minimum propagation delay .calculation of propagation delay
Views: 7502 sigjobs
Guidelines (VC) - 7
 
05:27
Gates-to RTL simulation .Problems related to mixed RTL and gate level simulation
Views: 599 sigjobs
OTG 1
 
04:13
history contributors why USB OTG Applications Goal of the specification Cable & Connectors OTG Specification Details Summary
Views: 320 sigjobs
FIFO 6
 
05:12
gray code counter style 2 .block diagram explanation .fifo partitioning with synchronized pointer comparison .fifo ram memory rtl code
Views: 3006 sigjobs
CMOS 16
 
03:55
CMOS- Complex gates,Transistor sizing,Design Techniques for larger Fan-in,Design techniques to reduce switching activity,Transmission gate
Views: 2394 sigjobs
Races and Hazards
 
07:41
Description on races and hazards , race around condition , types of races ,how to avoid races , static hazards and how to avoid it , dynamic hazards and how to avoid it
Views: 33097 sigjobs
RAM Basics 4
 
08:00
a DRAM cell DRAM module with refresh control SRAM and DRAM timing
Views: 5263 sigjobs
CMOS 6
 
02:57
MOS theory - Cutoff,Linear and Saturation region,Drain current equation.
Views: 2033 sigjobs
Mac Features 2
 
06:18
Interfacing to AES_128 CCM .CCM nonce construction .I(m) and I(a) Calculation .counter_mode Bx BLocks .Block B1 format .Encryption Ax Blocks .Continuation of WUSB_frames 1 file .Frame structure during 4_way handshake process ( command frame) .Data frames
Views: 126 sigjobs
Sequential Circuits(Sequential ) - 2
 
08:14
sr latch operation .d latch .characteristic equation .master slave d flip flop
Views: 4997 sigjobs
Sequential Circuits (Sequential) - 3
 
06:25
d flip flop .clear and preset .asynchronous inputs .master slave jk flip flop
Views: 2747 sigjobs
Metastability
 
04:48
Multiple Cycle Synchronizer De-skewed Multiple-Cycle Synchronizer
Views: 2072 sigjobs
Syestem Verilog 1-18
 
06:56
Description on Procedural blocks, tasks and functions,always procedural block,system verilog specialized procedural block
Views: 1350 sigjobs
CMOS 1
 
06:36
Introduction to CMOS technology, Introduction to silicon semiconductor technology,brief descriptions on wafer processing- czochralski method, oxidation,epitaxy, eposition, Ion-implantation, Diffusion.
Views: 11337 sigjobs
Asynchronous Circuit (async) - 3
 
05:10
design procedure .identify all states .write flow table .synthesize logic .race
Views: 2836 sigjobs
CMOS 2
 
03:37
Steps of fabrication process flow, Cross sectional view of nmos and pmos transistors.
Views: 10698 sigjobs

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